The present invention relates to a semiconductor memory device operable at a high speed.
With remarkable progress in recent semiconductor technology, a higher operating speed is required for the semiconductor memory device. An example of the prior memory device operating at a high speed is disclosed in Japanese Patent Application No. 57-138573, filed by the same applicant as that of the present invention. In the semiconductor memory device, a delay in the access time on the word line is reduced for speeding up the memory device operation. FIG. 1 shows an arrangement of such a memory device. In the figure, reference numerals 11, 11, . . . designate memory cells, respectively; SECT1 and SECT2 designate the first and second memory sections; 1WLi and 1WLi' designate the "i"th word lines in the memory sections SECT1 and SECT2; 2WLi designates the second word line in the "i"th line; RDi designates a row decoder of the "i"th line; BL1, BL1 to BLi, BLi and BL1', BL1' to BL1', BLi' designate bit lines; SSi and SSi' designate select switches for selecting the first word lines 1WLi and 1WLi' in the "i"th line in the memory sections SECT1 and SECT2, respectively; SD and SD' designate section decoders for controlling select switches SSi and SSi': SW1, SW1 to SWi, SWi and SW1', SW1' to SWi', SWi' designate switches for selecting bit lines controlled by the output of the column decoders CD1, . . . CDi and CDi', . . . CDi', D and D designate data lines; SA designates a sense amplifier; WR and WR designate write signals; and OUT designates an output signal.
In the semiconductor device thus arranged, in an access mode, the activated memory cells are only those connected to one of the first word lines 1WL1, . . . 1WLi, . . . , or one of the word lines 1WL', . . . 1WLi', . . . as defined by the row decoders RD1, . . . , RDi, . . . and the section decoder SD (or SD'). The remaining memory cells are not activated. This implies that the number of memory cells to be driven by a one row decoder may be reduced, and that an access time on the word line can be reduced. In fact, this semiconductor memory device is operable at a speed two to three times that of the conventional memory device.
FIGS. 2A and 2B respectively illustrate circuit arrangements of the switch SW1. The circuit arrangements of the other switches SW1-SWi, SWi-SW1, SW1' to SWi', SWi' are each the same as that of the switch SW1 with the exception of the bit lines. The switch in FIG. 2A comprises a MOSFET (metal oxide semiconductor field effect transistor) Q1 of an N channel type inserted between the bit line BLi and the data line D. The MOSFET Q1 is controlled by the output signal from the column decoder CD1. The switch in FIG. 2B comprises a transmission gate containing a couple of MOSFETs Q2 and Q3 of the N and P channel type. If necessary, a column sense amplifier may be connected between a bit line and its complementary bit line, for example, the bit lines BL1 and BL1.
FIG. 3 shows a circuit arrangement of one of the memory cells 11 in the memory device shown in FIG. 1. In FIG. 3, Q4 and Q5 designate MOSFETs as gate elements. MOSFET pairs Q6, Q7 and Q8, Q9 respectively form CMOS (complementary MOS) inverters 12 and 13. The inverters 12 and 13 are interconnected at the input terminals, thereby forming a latch circuit. The output terminal of the inverter 12 and the input terminal of the inverter 13 are connected to one end of the MOSFET Q4. The output terminal of the inverter 13 and the input terminal of the inverter 12 are connected to one end of the MOSFET Q5.
In the circuit arrangement of FIG. 1, the data lines D and D are respectively connected to ends of the switches SW1, SWi, SW1', SWi', and SW1, SWi, SW1', SWi'. With this connection, the data lines D and e,ovs/D/ are accompanied by a stray capacitance present between the substrate and the source, the substrate and the drain, or the substrate and the gate of each of the MOSFETs forming the switches, even if those switches are not in an ON state. This indicates a great stray capacitance of the data lines D and D, and provides a great delay in the signal on the data line.
The signal delay will be discussed referring to FIGS. 4A-4E.
Let it be assumed that at time t.sub.o, the second word line 2WLi is selected by the row decoder RDi. The potential on the second word line 2WLi rises at a high speed (FIG. 4A). Following this, the first word line 1WLi of the memory section SECT1 (or the first word line 1WLi' in the second memory section SECT2) also rises at a high speed (at time t1 in FIG. 4B). The potential on the bit line BLi (BLi) gently varies (FIG. 4C). The gentle variation of the potential arises from the fact that the switches SW1, SW1 to SWi, SWi or SW1', SW1' to SWi', SWi' are structured as shown in FIG. 2A or FIG. 2B, and when these switches are selected, the bit lines BLi and BLi are respectively connected to the data lines D and D, thereby increasing the stray capacitance associated therewith. The increased stray capacitance provides a gentle variation of the potential on the data lines D and D (FIG. 4D). It is for this reason that a potential level of the output signal OUT of the sense amplifier SA settles down at time t2 after a very long time elapses from the time t1 (FIG. 4E). If a switch containing the section sense and write amplifiers is used for the switches SW1, SW1 to SWi, SWi and SW1', SW1' to SWi', SWi', the bit lines BLi and BLi and the data lines D and D may be electrically separated from each other. Therefore, the potential change on the bit line BLi is relatively quicker as indicated by a broken line (FIG. 4C). The capacitance strayed in association with the data lines D and D is great, however. In this respect, the improvement of the operation speed of the memory device is still unsatisfactory.